Project Goals

List of project goals

Posted by Rafael Asenjo on October 26, 2022

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Posted by Rafael Asenjo on October 25, 2022

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Objectives

The CooTSIoT project is driven by co-design activities, the core of which is constituted by the development of new healthcare and smart agriculture monitoring applications that process online sensor data and extract some useful patterns from the data in real time using a battery powered ultra-low power system, that embeds the sensors and the needed computing resources. The applications of interest in this project include ambulatory long-term monitoring and personalized detection of different seizure types using wearables compatible with a normal social life, as well as early identification of water or pathogen stress in subtropical plantations (strawberry, avocado, mango) during critical periods of cultivation using sensors embedded on a SoC. In both scenarios, an anomaly detection method will be at the heart of the algorithms, and it must be designed carefully to be able to perform constant monitoring while minimizing energy consumption. The novelty of our approach is that our anomaly detection method will be based on a novel primitive called the Contrast Profile (CP) that the data mining community has demonstrated to be more accurate and robust for the discrimination of patterns in time series than previous related approaches. The main challenge that we address here is that we must develop an ultra-efficient Contrast Profile implementation able to perform the computation of motif/discords over the streaming data on the resource-constrained wearables or ultra-low power sensor-based devices, while ensuring low energy consumption and memory footprints. For it, we will develop an ultra-fast Learned Approximate Contrast Profile (LACP) that taking into consideration the computational power of the embedded device (FLOP/s), the available memory and the acquisition rate of new data in the input stream, will build a prediction function able to perform, in constant time, the motif/discord detection (and therefore, anomaly detection) over the new incoming substrings in real time with minimum energy consumption.

The co-design efforts will also require the optimization of SW layers, in particular the careful selection of the programming model and supporting runtime layer to best leverage the ultra-low power system that embeds the applications. The ultra-low power architectures that we target in this project include a multicore and optionally an embedded accelerator, and we think there is an opportunity to explore the potential of the lightweight parallel task paradigm on our targeted ULP heterogeneous systems, an exploration that has not yet been undertaken. Among other aspects, the parallel pattern suitable for each application and method must be selected, and the runtime system must be optimized to enable dynamic energy-aware task scheduling, as well as to take advantage of the available architecture capabilities related to power management.

Moreover, in this project we target ultra-low power SoC devices based on RISC-V multicore processors produced by the PULP project. Our aim is to get devices that work below ~10 mW, so the co-design strategy will also explore how to further optimize the platform design by combining SoC power management strategies such as power-gating and clock-gating during idle time, with memory banks scaling, as well as by integrating domain-specific accelerators to further reduce the energy consumption. Following the experience of our collaborators at ESL, we will implement a programable CGRA designed to execute the most computationally intense loops of our LACP function.

Detailed list of goals

  1. O1. Development of new healthcare and smart agriculture monitoring applications using an anomaly detection method based on the ultra-fast implementation of the novel Contrast Profile primitive, which we name as Learned Approximate Contrast Profile - LACP-. In the context of healthcare monitoring, we will focus on the early detection of epileptic seizures (customized for each patient), while in the context of smart agriculture monitoring we will seek the early detection of water-pathogen stress that may affect crop and fruit production.

  2. O2. Optimization of SW layers to best leverage the ultra-low power system that embeds the applications. We will investigate the potential of the lightweight parallel task programming model on our targeted ultra-low power heterogeneous prototypes. For it, we will consider SYCL, an open, standard-based, cross-platform abstraction layer based on modern C++ that enables code for SIMD units, multicore and accelerator architectures. One important issue at this level is the parallel pattern suitable for each application (sensor channel parallelization - parallel_pipeline -, window parallelization - parallel_wavefront -), or method (parallel_for, parallel_reduce, parallel_for_each, …), what we will explore in this objective considering oneTBB. For the applicable pattern, we will also explore the appropriate synchronization mechanisms and their impact in performance.

  3. O3. Design and optimization of ultra-low power architectures for our application-specific embedded implementations. In collaboration with Prof. Atienza ESL group, we will participate in the design and optimization of the ULP multi-core heterogeneous prototype based on the RISC-V cores from the PULP project, that the ESL group is developing for biomedical applications on wearables. We will take advantage of their already working simulation environment, which consist of an SDK to run RTL simulations on Modelsim to obtain cycle-accurate timings and MrWolf to estimate power consumption. In our project, using as a baseline the prototype already developed by the ESL group, we will first identify the main architectural parameters that enable the efficient execution of our monitoring applications, while at the same time minimizing the energy consumed during the acquisition periods. In particular, we will evaluate available features to adapt the performance of the prototype to the computational demands of each application while minimizing the energy consumption. For instance, by combining SoC power management strategies such as power-gating and clock-gating during idle time, along with memory banks scaling depending on the specific application.